1. Field of the Invention
The present invention relates to an insulated gate bipolar transistor (hereinafter referred to as IGBT) and, more particularly, to an IGBT having a high short-circuit withstandability (i.e., high short circuit SOA) and a high latch-up withstandability (i.e., high latch-up current) suitable for an inverter.
2. Description of the Background Art
In general, an IGBT device has a plurality of IGBT elements (hereinafter referred to as IGBT cells) connected in parallel, each of which may have a polygonal configuration, such as a square configuration, or a striped configuration. FIG. 1A is a plan view showing a square IGBT cell in a conventional N channel IGBT device, and FIG. 1B is a sectional view taken along line 1B--1B of FIG. 1A. As best shown in FIG. 1B, the IGBT cell includes a P collector layer 1, and an N.sup.+ buffer layer 2 and an N epitaxial layer 3 provided on the P collector layer 1 in this sequence. P base regions 4 are selectively formed in the surface of the N epitaxial layer 3 and, further, N emitter regions 5 are selectively formed in the surface of each of the P base region 4. Regions 6 in the vicinity of the surface of the P base region 4, between the surfaces of the N epitaxial layer 3 and N emitter regions 5, are defined as channel regions. Gate insulation films 7 are deposited on the channel regions 6. Each of the insulation films 7 also covers the N epitaxial layer 3 to be integrated in the adjacent IGBT cells. Gate electrodes 8 are formed of substance such as polysilicon on the gate insulation films 7. An emitter electrode 9 is formed of metal such as aluminum to be in electrically contact with both the P base layer 4 and the N emitter regions 5. In the IGBT device, all the gate electrodes 8 of the IGBT cells are electrically connected in common and all the emitter electrodes 9 of the IGBT cells are also electrically connected in common. A collector electrode 10 of metal is formed over the whole bottom surface of the P collector layer 1 to be integrated in all the IGBT cells.
An IGBT is a voltage control type transistor having a MOS gate configuration similar to a MOSFET, so that the IGBT is advantageous because of its simplified drive circuit. When a positive voltage is applied to the gate electrodes 8 under the state where a positive voltage is applied to the collector electrode 10 and a negative voltage is applied to the emitter electrodes 9, inversion layers appear in the channel regions 6 to allow electrons to move into the N epitaxial layer 3 from the N emitter regions 5. On the other hand, holes are injected into the N epitaxial layer 3 from the P collector layer 1 through the N.sup.+ buffer layer 2 which controls the injection of those holes, so that the conductivity modulation is caused in the N epitaxial layer 3. This results in a significant reduction of resistance in the N epitaxial layer 3. Therefore, an IGBT device has an advantage where an ON state resistance in the N epitaxial layer 3 does not have much effect even in the IGBT device of high breakdown voltage, although an ON state resistance in a layer corresponding to the N epitaxial layer 3 has much effect in a MOSFET device of high breakdown voltage. Because of these advantages, the IGBT has been noted as a device suitable for an inverter.
Meanwhile, as shown in FIG. 1B, there exists a parasitic thyristor formed of the P collector layer 1, the N epitaxial layer 3, the P base regions 4 and the N emitter regions 5 in the IGBT. When the parasitic thyristor once turns on, a voltage applied to the gate electrode 8 can go longer control the main current. This phenomenon is called latch-up. Once latch-up is caused, an excess current results in a thermal breakdown of the IGBT. Accordingly, it is important for the IGBT to have a high latch-up breakdown voltage.
The mechanism of occurrence of a latch-up will be described below. When hole current flows just below the N emitter regions 5, a voltage drop occurs because of resistances R laterally extending in each of the P base regions 4. When this voltage drop becomes higher than the built-in potential in a PN junction formed of the N emitter regions 5 and the P base region 4, the PN junction is forwardly biased so that electrons injected from the N emitter regions 5 to the P base regions 4. This provides trigger and results in latch-up. As the main current I.sub.C is increased, the hole current flowing just below the N emitter regions 5 is increased, so that a latch-up is easily caused. Hence, the IGBT design generally implemented so that I.sub.L &gt;I.sub.C(Sat)Max is satisfied, where I.sub.L is the limit of the main current to which latch-up can be avoided and I.sub.C(Sat)Max is a saturation current at the maximum gate voltage actually used.
FIG. 2 is a circuit diagram showing an inverter device in which six IGBTs 11a-11f are used as switching elements. In a usual inverter device, when arms are short-circuited, a current sensor 12 detects an excess current to force all the switching elements (the IGBTs 11a-11f in the circuit shown in FIG. 2) to be turned off so as to prevent those switching elements from breaking down. However, since such protecting function does not immediately work, those switching elements come to be subjected to an excess current for some time. Hence, it is important for the IGBT to have a high short-circuit breakdown voltage when it is incorporated into the inverter device as switching element.
In the IGBT shown in FIG. 1B, an electron current flowing in the channel region 6 serves as a base current I.sub.B of a PNP transistor formed of the P collector layer 1, the N epitaxial layer 3 and the P base regions 4. Assuming that h.sub.FE represents a current amplification factor of the PNP transistor, the main current I.sub.C =h.sub.FE .times.I.sub.B. No P collector layer 1 is in MOSFET. This means there is no amplification caused by the above mentioned PNP transistor in the MOSFET and, therefore, the above equation should be I.sub.C =I.sub.B. Thus, as shown in FIG. 3, a saturation current I.sub.C(Sat) of the IGBT, which is restricted by a channel resistance on the condition that a gate voltage is constant, is approximately h.sub.FE times as large as that of the MOSFET. The I.sub.C(Sat) corresponds to a self-restriction current in short-circuiting.
FIGS. 4(A)-4(C) are diagrams showing a wave form in an IGBT short-circuiting test. Herein, a gate pulse shown in FIG. 4(C) is applied to the Gate electrode 8 with power supply voltage being directly applied across the emitter electrode 9 and the collector electrode 10 of the IGBT without a load. As a result, a large main current I.sub.C (&lt;I.sub.C(Sat)) flows for a period of time t.sub.W, as shown in FIG. 4(B), with a high collector voltage V.sub.C being applied as shown in FIG. 4(A). When I.sub.C .times.V.sub.C .times.t.sub.W goes beyond a critical value, the IGBT is thermally broken down. This critical value is determined depending upon the area of an IGBT chip, the resistance value and the thickness of the N epitaxial layer 3 and the like. It is preferable that I.sub.C(Sat) is as small as possible, in order to enhance the short-circuit SOA. To easily satisfy the previously mentioned relationship that the latch-up critical main current I.sub.L &gt;I.sub.C(Sat)Max, also, the I.sub.C(Sat) may as well be small. However, it is impossible to make the I.sub.C(Sat) too small from an aspect of the conductive ability and in the ON state loss.
To enhance the latch-up breakdown voltage, that is, to make the latch-up critical main current I.sub.L large, emitter bypass structures shown in FIGS. 5 and 6 have been proposed. Sectional views taken along line 1B--1B of FIG. 5 and line 1B--1B of FIG. 6 are the same as in FIG. 1B. Since an N emitter region 5 is eliminated in a bypass region 13, the rate of a hole current flowing through a P base region 4 just below the N emitter region 5 is decreased. This supresses the occurrence of a latch-up. In the emitter bypass structure shown in FIG. 6, further, a channel width is somewhat reduced. This makes the I.sub.C(Sat) small more or less and results in the increase of the short-circuit SOA.
A conventional IGBT is structured as has been described, and it has been desired to enhance its latch-up current and short-circuit SOA. For that purpose, the emitter bypass structure has been proposed. However, the fact is that it does not bring a sufficient latch-up current and short-circuit SOA suitable for an actual application to an inverter device.